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[VHDL-FPGA-Verilog] hiervhdl

Description: Using Hierarchy in VHDL Design vhdl语言初学者的天堂-Using VHDL Design VHDL language beginners paradise
Platform: | Size: 44032 | Author: 土木文田 | Hits:

[VHDL-FPGA-Verilog] AEScoremodules

Description: AES decoder aes_dec.vhdl AES encoder aes_enc.vhdl Package used by rest of design aes_pkg.vhdl Key Expansion component for AES encoder and decoder key_expansion.vhdl -AES AES encoder decoder aes_dec.vhdl aes_ enc.vhdl Package used by rest of design aes_pkg . vhdl Key Expansion component for a AES encoder nd decoder key_expansion.vhdl
Platform: | Size: 10240 | Author: 许茹芸 | Hits:

[Crack Hack] 3des-VHDL

Description: 3des的VHDL实现，适用于quartus环境-3des VHDL applicable to the environment quartus
Platform: | Size: 95232 | Author: xin | Hits:

[Other] EMCRYPTCHIPFORFPGA

Description: 基于FPGA加密芯片设计论文（AES和DES算法）-FPGA-based encryption chip design thesis (AES and DES algorithm)
Platform: | Size: 1068032 | Author: David | Hits:

[VHDL-FPGA-Verilog] 3des_vhdl

Description: 3重DES（3DES）加密算法的问答及其VHDL实现。-3 re-DES (3DES) encryption algorithm and the Q
Platform: | Size: 140288 | Author: 张开文 | Hits:

[Crack Hack] mos_des

Description: 这是一个用VHDL语言实现了DES加密功能的程序，由于DES加密的模式，解密时需把密要倒置-This is a VHDL language with the DES encryption process, as a result of the mode of DES encryption, decryption is required to close to the inverted
Platform: | Size: 27648 | Author: liyajun | Hits:

[Crack Hack] DES_verilog

Description: this DES made by verilog
Platform: | Size: 15360 | Author: Shawn | Hits:

[Crack Hack] DES_Verilog

Description: 这是我用Verilog写的DES加解密程序,准确的说这是一份实验报告,里面不但有程序还有简单的注释[主要是针对仿真的波形的],我主要写的是主控部分,密钥生成部分参考了下版原康宏的程序.该程序即可加密也可解密,选用CycloneII器件即能跑到100Mhz以上.-This is what I used to write Verilog the DES encryption and decryption procedures, accurate to say that this is a test report, which not only have a simple Notes program [is mainly directed against the waveform simulation], I write is the main control part key generation is partly based on the next version of the original Yasuhiro procedures. The program can also be encrypted can be decrypted, CycloneII optional devices which can run more than 100Mhz.
Platform: | Size: 296960 | Author: jesse | Hits:

[VHDL-FPGA-Verilog] DES101

Description: 数据加密算法（Data Encryption Algorithm，DEA）的数据加密标准（Data Encryption Standard，DES）是规范的描述，它出自 IBM 的研究工作，并在 1997 年被美国政府正式采纳。它很可能是使用最广泛的秘钥系统，特别是在保护金融数据的安全中，最初开发的 DES 是嵌入硬 件中的。通常，自动取款机（Automated Teller Machine，ATM）都使用 DES。文件是DES代码的VHDL描述 -Data encryption algorithm (Data Encryption Algorithm, DEA) of the Data Encryption Standard (Data Encryption Standard, DES) is a standardized description of it from IBM s research work and, in 1997, formally adopted by the U.S. government. It is probably the most widely used secret key system, especially in protecting the safety of financial data, the initial development of DES is embedded in hardware. Usually, automated teller machines (Automated Teller Machine, ATM) are the use of DES. Document is described in VHDL code DES
Platform: | Size: 676864 | Author: 陈 | Hits:

[Crack Hack] DES

Description: DES算法的verilog实现，实现了硬件IC对DES的构架，可以直接应用在系统当中。-DES algorithm Verilog realized, the realization of the hardware IC framework of DES, can be directly used in the system.
Platform: | Size: 10240 | Author: 金鑫 | Hits:

[VHDL-FPGA-Verilog] DES_IP

Description: 有效的改进3-DES算法的执行速度，采用了多级流水线技术，设计了一种高速的硬件结构，使得原来需要48个时钟周期才能完成的运算，现在只需要一个时钟周期就可以完成。另外通过增加输入/输出的控制信号。使得该IP可以方便的集成到SOC中，大大缩短了SOC的设计周期。-Effective 3-DES algorithm to improve the implementation of speed, multi-stage pipeline technology, designed a high-speed hardware architecture, making the original 48 clock cycles required to complete the operation, and now only need one clock cycle can be completed. In addition by increasing the input/output control signal. Makes the IP can be easily integrated into the SOC, the SOC has significantly shortened the design cycle.
Platform: | Size: 23552 | Author: charity | Hits:

[VHDL-FPGA-Verilog] des

Description: this is des code of vhdl version.
Platform: | Size: 3072 | Author: bluedkdk | Hits:

[Crack Hack] DESCryptographicAlgorithm

Description: des加密算法,用于IP通讯方面的,用VHDL写成的源程序-des encryption algorithm used for IP communications.the source codes are written in VHDL
Platform: | Size: 28672 | Author: wy | Hits:

[VHDL-FPGA-Verilog] DES

Description: This is verilog source code for DES(Data Encryption standard) which is used in network security.
Platform: | Size: 20480 | Author: Krupesh | Hits:

[Crack Hack] DES_Encrypt_Decrypt_Verilog

Description: DES加密算法的Verilog HDL实现，带模式选择端口，可以实现加密和解密，已经modelsim仿真通过。-Des En/Decrypt,Verilog HDL code
Platform: | Size: 8192 | Author: Amazing_Eric | Hits:

[Crack Hack] DESsuanfa

Description: DES的加解密算法的实现，无错，非常适合毕业设计运用-DES encryption and decryption algorithm, error-free
Platform: | Size: 13312 | Author: longli | Hits:

[Crack Hack] topic

Description: DES加密算法的VHDL和VERILOG源程序- Xilinx开源共享61EDA代码工厂-DES encryption algorithm of VHDL and VERILOG source code- Xilinx factory open source code sharing 61EDA
Platform: | Size: 274432 | Author: renkaiqiang | Hits:

[VHDL-FPGA-Verilog] des

Description: des解密加密的verilog源代码其中包含有测试源代码，仿真结果图-verilog des decrypt encrypted source code which includes testing the source code, Simulation results
Platform: | Size: 343040 | Author: cong | Hits:

[VHDL-FPGA-Verilog] key

Description: 用vhdl语言实现des编码中的密钥产生 是des编码中重要的一部分-Des code using vhdl language in the key generation is an important part des coding
Platform: | Size: 1024 | Author: guosai | Hits:

[Software Engineering] des1

Description: 从万方数据库中下的介绍des加密以及解密的两片文章，是用FPGA实现的,pdf格式.希望对理解des加密以及解密的原理有所帮助。 -From the description of the database under the des encryption and decryption of the two articles is the use of FPGA implementation, pdf format. Hope to understand the principles of des encryption and decryption help.
Platform: | Size: 277504 | Author: chengpan | Hits:
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